The present invention relates generally to a large-scale integrated circuit device (hereafter referred to as LSI). More specifically, the invention relates to a LSI including a serial bus function for externally performing setting and changing internal functions through a serial bus and a boundary scanning function for performing checking of wiring after installation on a circuit board.
For externally setting and changing internal functions of the LSI, there has been proposed a method to vary a set value of an internal coefficient or so forth by the serial bus function as disclosed in Japanese Unexamined Patent Publication No. 1-205647. For instance, in case of the LSI for control, it is required to externally set a coefficient of an internal multiplier or to vary a delay amount for changing function of a circuit system, in which the LSI is installed. In such case, the above-mentioned serial bus function is used.
On the other hand, there are available LSIs incorporating the boundary scanning function as standardized by IEEE 1149.1. Such LSIs permits identification of a faulty portion by checking soldering failure, pattern failure, functions of the LSI per se by the boundary scanning function after installation on the circuit board.
FIG. 7 is a schematic block diagram of the LSI having the serial bus function. A serial/parallel converter 101 converts a serial data (SID) 109 externally input as an internal coefficient into a parallel data 110. The parallel data becomes an input for a plurality of registers 106 and 107. A register selector 105 generates a selection control signal 116 and 117 for determining the register to store the parallel data 110. The data (internal coefficient) 118 stored in one of the registers 106 and 107 is set in a LSI function block 1.
An address decoder 102 judges whether a main address is the address of the LSI per se when the parallel data 110 is a main address signal. When the address is the address of the LSI per se, a matching signal 111 becomes active and is outputted to a state controller 103. The state controller 103 uses the matching signal 111 and a bus busy signal (SIB) 112 and a clock signal (SIK) 113 as inputs, and generates an enabling signal 115 for enabling the register selector 105 in synchronism with the clock signal 113 when both of the matching signal 111 and the bus busy signal 112 are active.
A sub-address decoder 104 generates a selection signal for selecting one of a plurality of registers 106 and 107 through checking of a sub-address when the parallel data 110 is a sub-address signal, and outputs the sub-address signal to the register selector 105. The register selector 105 generates the above-mentioned selection control signal 116 and 117 on the basis of the selection signal 114 and the enabling signal 115.
FIG. 8 shows a timing chart illustrating an operation of the serial bus function. It should be noted, the right side end of each signal above the broken line is continued to the left side end of the corresponding signal.
Initially, when the bus busy signal 112 is turned into Low level, the serial bus function initiates operation. The serial data 109 in synchronism with the clock signal 113 is converted into the parallel data 110 by the serial/parallel converter 101. The parallel data 110 for main addresses A7.about.A0 as illustration in FIG. 8 is checked whether it is the address of the LSI per se or not by the address decoder 102. If the address is that of the LSI per se, the matching signal 111 becomes active. Then, the state controller 103 recognizes that the input signal on the data 109 input subsequently to the main address A7.about.A0 is for its own data to make the enabling signal 115 active for enabling the register selector 105.
In the sub-address decoder 104, check is performed for the subsequently supplied signals, such as sub-address and so forth, as input signal on the data 109 {R/W (indicative of the input direction), C0.about.C1 (chip select), S4.about.S0 (sub-address) of FIG. 8} for generating the selection signal 114 selecting one of the registers 106 and 107. Based on the signal designated by the sub-address, the register selector 105 generates the selection control signal 116, 117 for selecting the register. At this time, the serial data D7.about.D0 on the data 109 is stored in the selected register through serial/parallel conversion and thus the operation of the LSI function block is designated by the data (designation signal) 118.
For realizing such serial bus function, it becomes necessary to provide at least three terminals, i.e. a data input 109, a bus busy input 112 and a clock input 113, as shown in FIG. 7.
Next, the LSI having the boundary scanning function will be schematically illustrated in FIG. 9. A TAP controller 201 generates various signals 215, 216, 224 and 225 for controlling the boundary scanning function depending upon the state of a test mode signal (TMS) 213 which varies in synchronism with a test clock 214.
A test data (TDI) 212 is input as a serial data and output as a test data output (TDO) 227 based on operating conditions designated by the test access port (TAP) controller 201 through the following three paths. The first path is a path established through input/output cells 207, 208 provided between the LSI function block 1 and signal input/output, serial lines 219, 222, 226 to the test data output 227. The second path is a path established through a by-pass 205, serial lines 220, 222, 226 to the test data output 227. The third path is a path established through an instruction register 202, serial lines 223, 226 to the test data output 227.
Multiplexers 209 and 210 are adapted to select these three paths depending upon control signals 221 and 224. A buffer 211 is adapted to lead the output 226 of the multiplexer 210 to the test data output 227 depending upon a control signal 225.
It should be noted that an instruction decoder 203 decodes an instruction 217 from the instruction register 202 to generate a control signal 218 for a boundary register portion 204 and a control signal 221 for the multiplexer 209. Resistors 228 and 229 pull up the test data input 212 and the test mode signal 213, respectively.
Operation of the boundary scanning function is illustrated in FIG. 10 in a form of operational timing chart. In FIG. 10, the right side ends of the respective signal illustrated above the broken line are continued to the left side ends of the corresponding signals illustrated below the broken line.
Data IR of the test data input 212 is fed to the instruction register 202 in synchronism with the clock signal 214. At this time, TAP controller 201 generates an instruction register control signal 216 for controlling to write the instruction set by the data IR in the instruction register 202. The instruction 217 written in the instruction register 202 is output to the instruction decoder 203. The instruction decoder 203 outputs the control signal 218 to the boundary register portion 204 according to a timing signal 215 from the TAP controller 201.
After completion of instruction, the data DR on the test data input 212 is shifted to the input cell 207 and the output cell 208 in order. At this time, repeated operation of outputting designated data the output terminals of the input/output cells 207 and 208 and reading levels of input terminals connected to the output terminals. By this, solder failure, pattern breakage and so forth on the circuit board can be checked.
The multiplexers 209 and 210 are selected by the selection signals 221 and 224 as the outputs of the instruction decoder 203 and the TAP controller 201. The buffer 211 determines whether the test data output 227 is activated based on the enabling signal 225 of the TAP controller 201.
The important functions in this boundary scanning function are those in the input/out cells 207 and 208. The input/output cells 207 and 208 are provided between the LSI function block 1 and input/output pins (not shown) and are provided functions for controlling output data and sampling input data for detecting solder failure, pattern breakage on the circuit board.
For realizing this boundary scanning function, it is also required at least four terminals, i.e. the test data input 212, the test mode select signal 213, the test clock signal 216 and the test data output 227. Furthermore, although is not illustrated in FIG. 9, even when a test reset terminal may be employed.
The above-mentioned two functions are useful and mutually independent. Toward the future, LSIs having these two functions will be increased. However, on the other hand, for the LSI incorporating the serial bus function, at least three terminals are necessary, and for the LSI incorporating the boundary scanning function, at least four, but possible five terminals. Furthermore, when both functions are intended to be incorporated in LSI, at least seven, possibly eight terminals are required to be additional included. This results in increasing of the size of the LSI package. Furthermore, it is possible to inherently cause necessity of removal of useful terminals for installing the additional terminals. In addition, it becomes necessary to provide the wiring pattern adapted to the additional terminals and to cause difficulty in designing the layout.